1. Technical Field
The present invention relates to a delay locked loop (DLL) circuit and a method of controlling the same, and more particularly, to a DLL circuit and a method of controlling the same capable of shortening a clock delay locking time and reducing a device area.
2. Related Art
In general, DLL circuits are used to provide an internal clock, whose phase leads the phase of a reference clock, by converting an external clock by a predetermined amount of time. Generally, the internal clock is generated to operate in synchronization with data in a semiconductor memory apparatus having a high degree of integration, such as a Synchronous Dynamic Random Access Memory (SDRAM).
More specifically, when an external clock is input to a clock input buffer by an input pin, the clock input buffer generates an internal clock. Then, the internal clock controls a data output buffer which outputs data. The internal clock is delayed from the external clock by a predetermined amount of time by the clock input buffer, and the data output from the data output buffer is also delayed by a predetermined amount of time.
Therefore, the output data is delayed as compared with the external clock by a large amount of time. That is, the output data access time required to output data after the external clock is input is prolonged.
In order to solve this problem, a DLL circuit is used to make the phase of the internal clock lead the phase of the external clock by a predetermined amount of time. As a result, data is output without being delayed as compared with the external clock. That is, the DLL circuit receives an external clock and generates an internal clock whose phase leads the phase of the external clock by a predetermined amount of time, and the internal clock is used as a reference clock in, for example, a data output buffer.
Next, a DLL circuit according to the related art will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram of a DLL circuit according to the related art.
As shown in FIG. 1, a DLL circuit 1 includes: a clock buffer 10 that changes the amplitude of an external clock clk_ext, to generate a reference clock clk_ref; a delay unit 20 that delays the reference clock clk_ref in a push or pull manner in response to the input of a delay control signal dcl to generate a delay clock clk_dly, and transmits the generated delay clock clk_dly to a data output buffer 30 so as to synchronize with data transmitted from a memory cell; a delay compensating unit 40 that delays the delay clock clk_dly to generate a feedback clock clk_fb in order to compensate for a delay time produced by delay elements provided on a transmission path of the delay clock clk_dly to the outside of a semiconductor integrated circuit; a phase comparing unit 50 that compares the phase of the reference clock clk_ref with the phase of the feedback clock clk_fb to generate a phase comparison signal pcm; and a delay control unit 60 that generates the delay control signal dcl on the basis of the phase comparison signal pcm and transmits the delay control signal dcl to the delay unit 20.
When the external clock clk_ext is transmitted to the clock buffer 10 of the semiconductor integrated circuit having the DLL circuit 1, the clock buffer 10 changes the external clock clk_ext having a small amplitude into the reference clock clk_ref having a large amplitude, and transmits the reference clock clk_ref to the delay unit 20. Then, the delay unit 20 delays the reference clock clk_ref by a predetermined amount of time and outputs the delayed clock as the delay clock clk_dly.
The delay compensating unit 40 has pre-calculated delay values of delay elements provided on a path through which the delay clock clk_dly transmitted from the delay unit 20 is transmitted to the data output buffer 30. Therefore, the delay compensating unit 40 gives a predetermined delay time, for compensating for the delay values of the delay elements, to the delay clock clk_dly to generate the feedback clock clk_fb. Then, the phase comparing unit 50 detects the phase difference between the reference clock clk_ref and the feedback clock clk_fb to generate the phase comparison signal pcm. The delay control unit 60 generates the delay control signal dcl in response to the input of the phase comparison signal pcm to instruct the delay unit 20 to perform a push or pull delay operation. The delay unit 20 gives a positive or negative delay time to the reference clock clk_ref on the basis of the delay control signal dcl.
FIGS. 2A to 2C are timing charts illustrating the operation of the DLL circuit shown in FIG. 1.
The reference clock clk_ref, the feedback clock clk_fb, and a locked clock having a rising edge time identical to those of the reference clock clk_ref and the feedback clock clk_fb are shown in FIGS. 2A to 2C.
FIG. 2A shows the feedback clock clk_fb whose phase leads the phase of the reference clock clk_ref when the external clock clk_ext is a high-frequency signal. In this case, a phase difference Trf between the reference clock clk_ref and the feedback clock clk_fb is larger than a phase difference Tfl between the feedback clock clk_fb and the locked clock.
FIG. 2B shows the reference clock clk_ref whose phase leads the phase of the feedback clock clk_fb when the external clock clk_ext is a high-frequency signal. In this case, the phase difference Trf between the reference clock clk_ref and the feedback clock clk_fb is smaller than the phase difference Tfl between the feedback clock clk_fb and the locked clock. That is, in FIG. 2B, the phase difference Tfl between the feedback clock clk_fb and the locked clock is larger than that shown in FIG. 2A, and thus a larger amount of delay time should be given to the reference clock clk_ref until the phase difference Tfl between the feedback clock clk_fb and the locked clock is zero.
FIG. 2C shows the waveforms of the reference clock clk_ref and the feedback clock clk_fb when a low-frequency external clock clk_ext is input to the DLL circuit for generating the reference clock clk_ref and the feedback clock clk_fb. In this case, the phase difference Trf between the reference clock clk_ref and the feedback clock clk_fb is the same as shown in FIG. 2A. This is because the delay time given to the reference clock clk_ref by the delay unit 20 and the delay time given to the delay clock clk_dly by the delay compensating unit 40 are the same regardless of the frequency. However, the phase difference Tfl between the feedback clock clk_fb and the fixed clock is considerably larger than that shown in FIG. 2A. That is, when a low-frequency clock is input to the DLL circuit, a larger amount of delay time should be given to the reference clock clk_ref until the phase difference Tfl between the feedback clock clk_fb and the locked clock is zero.
As described above, in the delay locking operation of the DLL circuit with respect to the internal clock, when the phase of the reference clock leads the phase of the feedback clock, a larger amount of delay time is given to the reference clock compared to when the phase of the feedback clock leads the phase of the reference clock. In addition, the lower the frequency of the external clock becomes, the larger the amount of delay time to be given to the reference clock by the delay unit becomes. When the amount of delay time given to the reference clock becomes large, it takes the DLL circuit a lot of time to perform a clock delay locking operation, resulting in the deterioration of the efficiency of the DLL circuit. In order to give the larger amount of delay time to the reference clock, a larger number of delay elements should be provided in the delay unit, which results in an increase in the occupation area of DLL circuit.